In a projection-type exposure apparatus utilized in the manufacture of various devices, e.g., semiconductor chips such as IC and LSI chips, display elements such as liquid crystal panels, detecting elements such as magnetic heads, and image sensors such as CCDs, an increase in the fineness and density of the circuits used in these devices has been accompanied by the need to project a circuit pattern on the surface of a reticle onto the surface of a wafer, to thereby expose the wafer to the pattern, at a higher resolution.
Since the projection resolution of a circuit pattern depends upon the NA (numerical aperture) of the projection optical system and the wavelength of the exposing light, a method of enlarging the NA of the projection optical system or a method of shortening the wavelength of the exposing light has been adopted as a method of raising resolution. In relation to the latter method, a shift from g rays to i rays and from i rays to an excimer laser is in progress in regard to the exposing light source. Exposure systems based upon excimer lasers having lasing wavelengths of 248 nm and 193 nm have already been put into practical use.
Exposure systems of even shorter lasing wavelengths, namely a VUV exposure system that utilizes exposing light having a wavelength of 157 nm and an EUV exposure system that utilizes exposing light having a wavelength of 13 nm, are being studied as candidates for next-generation exposure systems.
Further, processes for manufacturing semiconductor devices have become highly diversified, and methods such as CMP (Chemical Mechanical Polishing) have been introduced as flattening techniques for solving the problem of inadequate focal depth encountered in exposure systems.
Structures and materials of semiconductor devices also are multifarious. For example, a P-HEMT (Pseudomorphic High Electron Mobility Transistor) and an M-HEMT (Metamorphe-HEMT), which are obtained by combining compounds such as GaAs and InP, etc., and an HBT (Heterojunction Bipolar Transistor), which employs SiGe or SiGeC, have been proposed.
Meanwhile, finer circuit patterns have led to the need for highly precise alignment of the reticle, on which the circuit pattern is formed, and the wafer, onto which the circuit pattern is projected. The required precision is ⅓ of the circuit line width. For example, the required precision in current 180-nm designs is 60 nm, or ⅓ of 180.
Alignment in an exposure apparatus is carried out by exposing a wafer to the circuit pattern on a reticle and alignment marks simultaneously to transfer the circuit pattern and alignment marks, detecting the position of the alignment marks optically when the wafer is exposed to the circuit pattern of the next reticle, and positioning the wafer with respect to the reticle. Methods of detecting an alignment mark include a method of capturing the image of the alignment mark upon enlarging the image by a microscope, and then detecting the position of the mark image, and a method of using a diffraction grating as an alignment mark, detecting the phase of an interference signal that interferes with the diffracted light, and detecting the position of the diffraction grating.
The state of the art in the semiconductor industry is such that raising overlay accuracy for aligning the design pattern of the next step and the circuit pattern already on the wafer is essential for the purpose of improving the performance of semiconductor devices and the yield of manufacture insofar as an exposure apparatus is used. However, owing to the introduction of special semiconductor manufacturing techniques such as the CMP process, the structure of circuit patterns has been improved but a frequently occurring problem is the occurrence of a variation in the shape of the alignment marks between wafers or between shots and an attendant decline in alignment precision.
This is caused by the fact that an increase in the fineness of circuit patterns is accompanied by an increase in the difference between the line width of the circuit pattern and the line width of the alignment mark. In another words, the above problem arises because process conditions relating to film formation, etching and CMP, etc., are optimized to the line width of a fine circuit pattern (a line width of 0.1 to 0.15 μm), and therefore, with an alignment mark having a large line width (a line width of 0.6 to 4.0 μm), in many cases the process conditions are not appropriate.
When it is attempted to make the line width of an alignment mark conform to the line width of a circuit pattern, there is a decline in signal strength or contrast because the resolution of the detection optical system used in alignment is inadequate. The result is a decline in the stability of the alignment-mark detection signal. In order to realize a detection optical system capable of detecting an alignment mark having a line width equivalent to that of a circuit pattern, a large NA and a light source having a short wavelength are required. This necessitates a detection optical system equivalent to that of a projection optical system and therefore gives rise to a new problem, namely an increase in the cost of the apparatus.
FIG. 18 is a diagram illustrating alignment marks that have been acquired in a semiconductor manufacturing process.
After a reticle and wafer have been aligned in such a manner that a circuit pattern on the reticle will be transferred to the center of alignment marks 101, 102, 103 and 104 on the wafer in FIG. 18, a resist pattern 105 is formed through exposure and development steps. A method of detecting alignment-mark position along the Y direction in FIG. 18 will be described as an example. Specifically, an average value Ym1 of a position intermediate the positions of the alignment marks 101 and 103 and a deviation in the position of a cent r point Ym2 of a resist mark 105 are detected. Here the alignment-mark image processing range is as illustrated. Position information regarding the marks 101 and 103 is calculated after this area is integrated along the non-detection direction (the X direction).
Accordingly, if the alignment marks have unevenness, as shown in FIG. 18, averaging is achieved to a certain extent over the image processing range but an error occurs in a case where amount of deviation relative to the resist pattern is calculated.
In view of these circumstances, efforts have been made to change process conditions so as to thereby obtain conditions suited to both the alignment mark and circuit pattern. To achieve this, conditions are set by trial and error, or various types of alignment marks having different line widths are fabricated, exposure is evaluated and use is made of the alignment mark whose line width is deemed to be best.
Accordingly, an enormous amount of time is required to decide the optimum conditions (parameters). Further, a process error, for example, may occur after parameters have been decided. In such case it may be necessary to alter the parameters of the exposure apparatus to follow up a modification in the manufacturing process in response to the process error. Altering the parameters takes a great deal of time.
In the future, moreover, further progress will be made in producing finer circuit patterns, new semiconductor processes will be introduced and wafers of larger diameter (on the order of 300 mm) will be used. As a result, it is predicted that it will be increasingly difficult to fabricate both circuit patterns and alignment marks that are defect-free over the entire surface of a wafer.